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Marios Papaefthymiou

Marios Papaefthymiou is Professor of Computer Science and the Ted and Janice Smith Family Foundation Dean in the Donald Bren School of Information and Computer Sciences at the University of California, Irvine. Prior to UC Irvine, he held faculty positions in Electrical Engineering and Computer Science at the University of Michigan, where he also served as chair of the Computer Science and Engineering Division, and at Yale University.

Papaefthymiou is interested in the design of energy-efficient computers. Together with his students at Michigan, he has pioneered the exploration of charge-recovery (a.k.a. adiabatic or energy-recycling) technologies, demonstrating over the span of two decades numerous charge-recovery silicon prototypes that achieve substantial (sometimes order of magnitude) energy savings over their conventional counterparts.  He has also pioneered the commercialization of charge-recovery technologies, co-founding Cyclos Semiconductor to develop charge-recovery design solutions for energy-efficient high-performance clocking.  The Cyclos technology marks the first-ever successful deployment of charge-recovery in high-volume commercial products and has been used in multi-GHz server chips from AMD and IBM.

In addition to energy-efficient design, Papaefthymiou has made contributions to the design and optimization of high-performance digital systems, with a focus on asymptotically efficient retiming algorithms.  He has also contributed to other areas of electronic design automation, including algorithms and tools for power estimation and design complexity management.

Papaefthymiou has co-authored award-winning papers published at flagship venues in computer architecture and electronic design automation. Among other distinctions, he has received the Arthur Greer Memorial Prize for Outstanding Scholarly Publication or Research from Yale College, the Outstanding Achievement Award from the EECS Department at U. Michigan, the Ted Kennedy Family Faculty Team Excellence Award from the College of Engineering at U. Michigan, the Faculty Recognition Award from the Graduate School at U. Michigan, a Young Investigator Award from ARO, CAREER and ITR Awards from NSF, and multiple IBM Faculty Partnership Awards.  He has been elected IEEE Fellow for contributions to the design of adiabatic circuits for high-performance computing.  His research has been supported by NSF, ARO, DARPA, SRC, Broadcom Foundation, IBM, and Intel.


Ph.D., Electrical Engineering and Computer Science, Massachusetts Institute of Technology, 1993

S.M., Electrical Engineering and Computer Science, Massachusetts Institute of Technology, 1990

B.S., Electrical Engineering, California Institute of Technology, 1988

Select Publications

  • H.-S. Wu, Z. Zhang, M. Papaefthymiou, “A 0.23mW heterogeneous deep-learning processor supporting dynamic execution of conditional neural networks,” European Solid-State Circuits Conference, September 2018.
  • H.-S. Wu, Z. Zhang, M. Papaefthymiou, “A 13.8µW binaural dual-microphone digital ANSI S1.11 filter bank for hearing aids with zero short-circuit-current logic in 65nm CMOS,” International Solid-State Circuits Conference, February 2017.
  • T.-C. Ou, Z. Zhang, M. Papaefthymiou, “A 934MHz 9Gb/S 3.2pJ/B/Iteration charge-recovery LDPC decoder with in-package inductor,” Asian Solid-State Circuits Conference, November 2015.
  • S. Lu, Z. Zhang, M. Papaefthymiou, “1.32GHz high-throughput charge-recovery AES core with resistance to DPA attacks,” IEEE Symposium on VLSI Circuits, June 2015.
  • T.-C. Ou, Z. Zhang, M. Papaefthymiou, “An 821MHz 7.9Gb/s 7.3pJ/b/iteration charge-recovery LDPC decoder,” International Solid-State Circuits Conference, February 2014.
  • A. Raghavan, Y. Luo, A. Chandawalla, M. Papaefthymiou, K. Pipe, T. Wenisch, M. Martin, “Computational sprinting,” 18th IEEE International Symposium on High Performance Computer Architecture, February 2012. Best Paper Award.
  • V. Sathe, S. Arekapudi, C. Ouyang, M. Papaefthymiou, A. Ishii, and S. Naffziger, “Resonant clock design for a power-efficient high-volume x86-64 microprocessor,” International Solid-State Circuits Conference, February 2012.

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