CS152: Computer Systems Architecture

2021 Winter

"People who are really serious about software should make their own hardware"
-- Alan Kay

Overview

In this course, we will cover how modern processors are designed to achieve high performance under which restrictions, and actually get hands-on experience with hardware design using a sequence of gently guided labs. You will get to see your ideas actually improve performance on real metal!
We will use RISC-V, a modern, real-world, and open-source ISA as our learnig tool.

Lecturer: Sang-Woo Jun
Time:

• Lecture: Tuesdays and Thursdays, 11:00 AM - 12:20 PM
• Discussion: Fridays, 1:00 PM - 1:50 PM

Location: Zoom

Topics Covered

• Instruction sets and abstraction
• Computer Arithmetic
• Pipelining and Hazards
• Memory Hierarchy
• Introduction to modern topics

Announcements

• 2020-12-22: Lectures will start on Tuesday, January 5th!

Material

• Lecture 1: Introduction [video] [slides]
• Lecture 1.5: Moore's Law [video] [slides]
• Lecture 2: HW-SW Interface [slides]
  • Lecture 2.1: HW-SW Interface [video]
  • Lecture 2.2: Good ISA [video]
  • Lecture 2.3: RISC and CISC [video]
• Lecture 3: RISC-V Assembly [slides]
  • Lecture 3.1: RISC-V Introduction [video]
  • Lecture 3.2: RISC-V Assembly [video]
  • Lecture 3.3: RISC-V ISA Encoding [video]
  • Lecture 3.4: Programming With RISC-V Assembly [video]
• Lecture 3.5: Storytime: x86 And Surrounding History [slides] [video]
• Lecture 4: Circuits Recap [slides]
  • Lecture 4.1: Digital Circuits, Why And How [video]
  • Lecture 4.2: Digital Circuits And Constraints[video]
• Lecture 5: Processor Microarchitecture [slides]
  • Lecture 5.1: Pipelining Concepts [video]
  • Lecture 5.2: Processor Pipelining Basics [video]
  • Lecture 5.3: Achieving Correct Pipelining - Data Hazards [video]
  • Lecture 5.4: Achieving Correct Pipelining - Control Hazards And Branch Prediction [video]
• Lecture 6: Processor Hands-On [slides]
  • Lecture 6.1: Processor Prototyping with FPGAs [video]
  • Lecture 6.2: Bluespec introduction [slides] [video]
  • Lecture 6.3: Pipelining hands-on [video]
  • Lecture 6.4: Pipelining hands-on continued [video]
• Lecture 7: Some loose topics [slides] [video]
• Lecture 8: Caches [slides]
  • Lecture 8.1: Caches introduction [video]
  • Lecture 8.2: Caches continued [video]
  • Lecture 8.3: Cache-optimized software example [video]
• Lecture 9: Architectural support for operating systems [slides]
  • Lecture 9.1: Privileges and exceptions [video]
  • Lecture 9.2: Exceptions and system calls [video]
• Lecture 10: Virtual memory [slides]
  • Lecture 10.1: Virtual memory 1 [video]
  • Lecture 10.2: Virtual memory 2 [video]
• Lecture 11: Multiprocessing [slides] [video]
• Lecture 12: SIMD and GPUs [slides]
  • Lecture 12.1: SIMD [video]
  • Lecture 12.2: GPU [video]
• Lecture 13: Systems, Storage [slides]
  • Lecture 13.1: System bus [video]
  • Lecture 13.2: Storage [video]

Labs

1. RISC-V Assembly handout sudoku.s emulator slides c implementation partial asm
2. Processor pipelining Virtualbox VM instructions
   • Note! The processor code repository has changed! Instead of running the provided clone script, please clone this:
     https://github.com/sangwoojun/ulx3s_bsv.git

Grading

• Three Labs: 60 %
• Final: 40 %

Book

This class does not have a mandatory book.
However, it may be helpful to consult Computer Organization and Design RISC-V Edition: The Hardware Software Interface (by David A. Patterson and John L. Hennessy).

Interesting Materials

• The Digital Antiquarian, "Doing Windows" Series [link]: A fascinating history of how Microsoft Windows became what others couldn't, and how innovations in Intel 80386 helped made it happen.
• RISC-V ISA reference [link]
• Scott Meyers: Cpu Caches and Why You Care [link: Some less obvious but serious effects of memory access patterns on performance