Some News
2024-07-17: Collaboration project with Samsung has started for elastic in-memory compute units
2023-01-01: We are part of the $50.5M center for near-storage and near-memory computing research with the Semiconductor Research Corporation!
2021-10-26: UCI ICS wrote an article about our best paper in FPL, which involves a high school research assistant! [
link]
2021-03-27: Collaboration project with Samsung has started for cost-effective neural network acceleration on Smart SSDs
2020-12-22: Collaboration project with vmware is continuing into its third year!
2019-07-31: Collaboration project with vmware has started for flash storage management with near-storage acceleration
2019-06-05: NSF proposal for elastically allocated FPGAs in the cloud has been funded
2018-06-06: "
Thanks for the memories", The Next Platform's article on my research
Assistant professor at the
Computer Science Department
Donald Bren School of Information and Computer Sciences
University of California, Irvine
Contact: swjun _AT_ ics.uci.edu
Before joining UC Irvine in 2018, I earned my Ph.D. in Electrical Engineering and Computer Science at the Massachusetts Institute of Technology (2018), working with Professor Arvind.
I have earned my B.S. in Electrical and Computer Engineering at Seoul National University (2010).
Research Interests
My research is in
innovative system architectures for low-cost high-performance computing.
My two prominent tools right now are
Non-Volatile Memory (NVM) and
reconfigurable hardware accelerators.
Software Distributions
- libsortreduce Library implementing the Sort-Reduce algorithm for sequentializing random updates into secondary storage, introduced in the GraFBoost paper.
- GraFBoost / BigSparse Graph analytics platform for handling very large graphs quickly using secondary storage, built using libsortreduce.
- BluespecPCIe High-performance PCIe library for the Xilinx 7 series FPGAs in the Bluespec language, including hardware core and software library.
Teaching
External Resources
Publications
My Google Scholar Profile
- 2024: Our paper on a flexible hardware accelerator for genome motif discovery has been accepted to eScience 2024
- 2024: Our paper on a hardware accelerator for plagiarism detection has been accepted to ACM Asia-Pacific Workshop on Systems (ApSys) 2024
- 2024: Our paper on extremely low-power vision inference for remote wildfire detection accepted to International Symposium on Low Power Electronics and Design (ISLPED) 2024!
- 2024: Our paper on an asynchronous interface for graph analytics on near-storage accelerators have been accelpted to Design Automation Conference (DAC) 2024
- 2024: Our paper on elastic allocation of accelerator peripherals has been published in Design Automation and Test in Europe (DATE) 2024
- 2023: Our paper on a near-storage accelerator for large-scale graph neural network tranining will be published at the International Conference on Parallel Architectures and Compilation Techniques (PACT) 2023
- 2023: Our paper on a near-storage accelerator for graph analytics have been selected in the ISCA@50 retrospective, which selects 100-ish papers of interest from ISCA over the past 25 years! [link]
- 2022: Our paper on memory-efficient hardware accelerator for bloom filter construction has been published at the International Conference on Field-Programmable Logic and Applications (FPL) 2022
- 2022: Our paper on very low-power hardware accelerators for floating-point PID controllers has been published at the (International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies) HEART 2022
- 2022: Our paper on hardware accelerators for weight and feature map compression of embedded neural networks has been published at MDPI Electronics 2022
- 2022: Our paper on floating-point compression for scientific simulation acceleration has been published at the Transactions on Reconfigurable Technology and Systems (TRETS) 2022
- 2021: Our paper on a near-storage accelerator for unstructured log analytics has been accepted to the International Symposium on Microarchitecture (MICRO) 2021
- 2021: Our IoT acceleration paper at FPL has been voted a Best Paper!
- 2021: Our paper on extremely low power (17 mW !) accelerator for recurrent neural networks on IoT devices has been accepted to the International Conference on Field-Programmable Logic and Applications (FPL) 2021
- ...
Recent Publications
[
link to list]