VHDL Reference Guide - While and Infinite Loop

**While and Infinite Loop**

Sequential Statement	---- used in ---->	Process Function Procedure

Syntax

while condition loop
   sequential statements
end loop;

loop
    sequential statements
end loop;

See LRM section 8.8

Rules and Examples

The while loop repeats the enclosed sequence of statements if the condition tested is true. The condition is tested before wach iteration.

process (A)
    variable I :
      integer range 0 to 4;
begin
    Z <= "0000";
    I := 0;
    while (I <= 3) loop
      if (A = I) then
        Z(I) <= '1';
      end if;
      I := I + 1;
    end loop; 
end process;

While loops may be useful in test benches:

process
begin
  while NOW < MAX_SIM_TIME loop
    CLK <= not CLK ;
    wait for PERIOD/2;
  end loop;
  wait;
end process;

To prevent simulation hang-up an infinite loop should usually contain at least one wait or exit statement:

process (A)
  variable I :
    integer range 0 to 4;
begin
  Z <= "0000";
  I := 0;    
  L1: loop
    exit L1 when I = 4;
    if (A = I) then
       Z(I) <= '1';
    end if;
    I := I + 1;
  end loop;    
end process;

Synthesis Issues

While and infinite loops are supported by some logic synthesis tools, with certain restrictions.

Whats New in '93

The while and infinite loop statements have not changed in VHDL-93.