VHDL MINI-REFERENCE

See the VHDL Language Reference Manual (VLRM) for Additional Details

I.      Primary Design Unit Model Structure
        A.    Entity Declaration Format
        B.    Architecture
II.    Packages
        A.    Declaration and Libraries
        B.    Identifiers, Numbers, Strings, and Expressions
        C.    Data Types
        D.    Objects: Signals, Constants, and Variables
        E.    Concurrent Statements
                1)        Signal Assignment
                2)        Process Statement
                3)        Block Statement
                4)        Procedure Statement
                5)        Component Instantiation
                6)        Concurrent Assertion
                7)        Generate Statement
        F.    Sequential Statements
                1)        Wait Statement
                2)        Signal Assignment
                3)        Variable Assignment
                4)        Procedure Call
                5)        Conditional Statements
                6)        Loop Statements
                7)        Procedure Statement
                8)        Function Statement
        G.    Other IEEE "std.logic" Functions
        H.    Object Attributes
        I.     The TEXTIO Package

PRIMARY DESIGN UNIT MODEL STRUCTURE - Back To Top

Entity Declaration Format - Back To Top

    entity  name  is
        port( port definition list );-- input/output signal ports
        generic( generic list);   -- optional generic list
    end name;

The mode of a port defines the directions of the singals on that pirt, and is one of: in, out, buffer, or inout.

Port Modes:

An in port

can be read but not updated within the module, carrying information into the module. (An in port cannot appear on the left hand side of a signal assignment.)

An out port

can be updated but not read within the module, carrying information out of the module. (An out port cannot appear on the right hand side of a signal assigment.)

A buffer port

likewise carries information out of a module, but can be both updated and read within the module.

An inout port

is bidirectional and can be both read and updated, with multiple update sources possible.

Example

   entity counter is
        port (Incr, Load, Clock: in     bit;
              Carry:             out    bit;
              Data_Out:          buffer bit_vector(7 downto 0);
              Data_In:           in     bit_vector(7 downto 0));
   end counter;

Example

    entity and_gate is
        port(a,b: in  bit;
             c:   out bit);
        generic (gate_delay: time := 5ns);
    end and_gate;

Architecture - Back To Top

  architecture arch_name of entity_name is
       ...  declarations ...
   begin
       ...  concurrent statements  ...
   end

• Behavioral Model: No structure or technology implied. Usually written in sequential, procedural style.
• Dataflow Model: All datapaths shown, plus all control signals.
• Structural Model: Interconnection of components.

VHDL PACKAGES - Back To Top

Package declaration format:

   package package_name is
     ... exported constant declarations
     ... exported type declarations
     ... exported subprogram declarations
   end package_name;

Example:

    package ee530 is
       constant maxint: integer := 16#ffff#;
       type arith_mode_type is (signed, unsigned);
       function minimum(constant a,b: in integer) return integer;
    end ee530;

Package body format:

   package body package_name is
       ... exported subprogram bodies
       ... other internally-used declarations
   end package_name;

Example:

   package body ee530 is
      function minimum (constant a,b: integer) return integer is
         variable c: integer; -- local variable
             begin
                if a < b then
                    c := a;  -- a is min
                else
                    c := b;  -- b is min
                end if;
                return c;  -- return min value
             end;
    end ee530;

Package Visibility

Example:

   use library_name.package_name.all

User-Developed Packages

    use package_name.all;

Example

   library lib_name;            -- make library visible
   use lib_name.pkg_name.all;   -- make package visible

VHDL Standard Packages

STANDARD - basic type declarations (always visible by default)
TEXTIO - ASCII input/output data types and subprograms

IEEE Standard 1164 Package

   library ieee;      -- VHDL Library stmt
      use ieee.std_logic_1164.all;

Special 12-valued data types/functions to interface with QuickSim II and schematic diagrams.

   library mgc_portable;            -- Special Mentor Graphics Library
   use mgc_portable.qsim_logic.all; -- Quicksim portable data types

VHDL IDENTIFIERS, NUMBERS, STRINGS, AND EXPRESSIONS - Back To Top

Identifiers

Examples

     Memory1, Adder_Module, Bus_16_Bit

Numeric Constants

Format: base#digits# -- base must be a decimal number

Examples

     16#9fba#           (hexadecimal)
     2#1111_1101_1011#  (binary)
     16#f.1f#E+2        (floating-point, exponent is decimal)

Bit String Literals

Examples

     x"ffe"            (12-bit hexadecimal value)
     o"777"            (9-bit octal value)
     b"1111_1101_1101" (12-bit binary value)

Arithmetic and Logical Expressions

• Logical: and, or, nand, nor, xor, not (for boolean or bit ops)
• Relational: =, /=, <, <=, >, >=
• Arithmetic: +, -, *, /, mod, rem, **, abs

(a mod b takes sign of b, a rem b takes sign of a)
• Concatenate: &

(ex. a & b makes one array)

Examples

   a <= b nand c;
   d := g1 * g2 / 3;
   Bus_16 <= Bus1_8 & Bus2_8;

VHDL DATA TYPES - Back To Top

Predefined Scalar Data Types (single objects)

VHDL Standard:

• bit values: '0', '1'
• boolean values: TRUE, FALSE
• integer values: -(231) to +(231 - 1) {SUN Limit}
• natural values: 0 to integer'high (subtype of integer)
• positive values: 1 to integer'high (subtype of integer)
• character values: ASCII characters (eg. 'A')
• time values include units (eg. 10ns, 20us)

IEEE Standard 1164 (package ieee.std_logic_1164.all)

• std_ulogic values: 'U','X','1','0','Z','W','H','L','-'
'U' = uninitialized
'X' = unknown
'W' = weak 'X'
'Z' = floating
'H'/'L' = weak '1'/'0'
'-' = don't care
• std_logic resolved "std_ulogic" values
• X01 subtype {'X','0','1'} of std_ulogic
• X01Z subtype {'X','0','1','Z'} of std_ulogic
• UX01 subtype {'U','X','0','1'} of std_ulogic
• UX01Z subtype {'U','X','0','1','Z'} of std_ulogic

Predefined VHDL Aggregate Data Types

• bit_vector array (natural range <>) of bit
• string array (natural range <>) of char
• text file of "string"

IEEE Standard 1164 Aggregate Data Types

• std_ulogic_vector array (natural range <>) of std_ulogic
• std_logic_vector array (natural range <>) of std_logic

Examples

    signal dbus: bit_vector(15 downto 0);
    dbus (7 downto 4) <= "0000"; (4-bit slice of dbus)
    signal cnt:  std_ulogic_vector(1 to 3);
    variable message: string(0 to 20);

User-Defined Enumeration Types

Example

   type opcodes is (add, sub, jump, call);  -- Type with 4 values
   signal instruc: opcodes;                 -- Signal of this type
     ...
   
   if instruc = add then   -- test for value 'add'
     ...

Other user-defined types

• Constrained array: Upper and lower indexes are specified.

Example

   type word is array (0 to 15) of bit;

• Unconstrained array: Indexes are specified when a signal or variable of that type is declared.

Examples

   type memory is array (integer range <>) of bit_vector(0 to 7);
  -- a type which is an arbitrary-sized array of 8-bit vectors
   variable memory256: memory(0 to 255); -- a 256-byte memory array
   variable stack: memory(15 downto 0);  -- a 16-byte memory array

• Subtype: A selected subset of values of a given type. Elements of different subtypes having the same base type may be combined in expressions (elements of different types cannot). Subtypes can be used to detect out-of-range values during simulation.

Examples

   subtype byte_signed is integer range -128 to 127;
   subtype byte_unsigned is integer range 0 to 255;

Aliases

Example

   signal instruction: bit_vector(31 downto 0);
   alias opcode: bit_vector(6 downto 0) is instruction(31 downto 25);
    ...
   opcode <= "1010101";  -- Set the opcode part of an instruction code

VHDL OBJECTS: CONSTANTS, VARIABLES, AND SIGNALS - Back To Top

Constants

constant symbol: type := value;

Examples

  constant  Vcc:  signal:= '1';   --logic 1 constant
  constant  zero4: bit_vector(0 to 3) := ('0','0','0','0');

Variables

variable symbol: type [:= initial_value];

Examples

   process
       variable count: integer  := 0;
       variable rega: bit_vector(7 downto 0);
   begin
       ...
       count := 7;      -- assign values to variables
       rega  := x"01";
       ...
   end;

Signals

Signals are declared via signal declaration statements or entity port definitions, and may be of any data type. The declaration syntax is:

signal sig_name: data_type [:=initial_value];

Examples

    signal clock: bit;
    signal GND:   bit := '0';
    signal databus: std_ulogic_vector(15 downto 0);
    signal addrbus: std_logic_vector(0 to 31);

signal line x

10ns '0' Driver of

20ns '1' signal x

Event Values

Times

Examples

    clock   <= not clock after 10ns;      -- change at T + 10ns
    databus <= mem1 and mem2 after delay; -- change at T + delay
    x       <= '1';                       -- change to '1' at time T + "delta";

• Inertial delay: The addition to an event queue of an event scheduled at time T automatically cancels any events in the queue scheduled to occur prior to time T, i.e. any event shorter than the delay time is suppressed.
• Transport delay: Each new event is simply inserted into the event queue, i.e. behavior is that of a delay line. The keyword transport is used to indicate transport delays.

Examples

    B <= A after 5ns;            -- inertial delay
    C <= transport A after 5 ns; -- transport delay

             5______15 17_________30
    A _______|       |_|          |_____________ 
                  ____________________
    B ___________|                    |_________ (Inertial Delay)
                  _______   __________
    C ___________|       |_|          |_________ (Transport Delay)
                10      20 22         35

NOTE: The std_logic and std_logic_vector types from the ieee library have predefined resolution functions:

Example

    signal data_line: std_logic;
    begin
      block1:  
          data_line <= '1';     -- one driver
          ...
      block2:
          data_line <= 'Z';  -- 2nd driver

CONCURRENT STATEMENTS - Back To Top

Concurrent Signal Assignment

1. A <= B; A <= B when condition1 elseC when condition2 else D when condition3 else E;
2. with expression select A <= B when choice1, C when choice2, D when choice3, E when others;

Examples

    A <= B after 10ns when condition1 else
         C after 12ns when condition2 else
         D after 11ns;

    -- 4-input multiplexer (Choice is a 2-bit vector)
    with Choice select 
         Out <=  In0 after 2ns when "00",
                 In1 after 2ns when "01",
                 In2 after 2ns when "10",
                 In3 after 2ns when "11";

    -- 2-to-4 decoder (Y = 4-bit and A = 2-bit vectors)
    Y <= "0001" after 2ns when A = "00" else
         "0010" after 2ns when A = "01" else
         "0100" after 2ns when A = "10" else
         "1000" after 2ns ;

    -- Tri-state driver: (Y is logic4; X is bit_vector)
    Y <= '0' after 1ns when En = '1' and X = '0' else
         '1' after 1ns when En = '1' and X = '1' else
         'Z' after 1ns;

    -- A is a 16-bit vector
    A <= (others => '0');   -- set all bits of A to '0'

Process Statement - Back To Top

Syntax:

    label: process (sensitivity list)   
           ... local declarations ...    
           begin
           ... sequential statements ...
           end process label;

Example

   DFF: process (clock)
          begin
             if clock = '1' then
                Q  <= D after 5ns;
                QN <= not D after 5ns;
             end if;
        end process DFF;

Block Statement - Back To Top

Syntax:

   label: block (guard expression)
          ... local declarations ...
          begin
          ... concurrent statements ...
          end block label;

Examples

    -- D Latch: Transfer D input to Q output when Enable = '1' 
    block (Enable = '1')
    begin
       Q <= guarded D after 5ns;

    end block;

    -- D Flip-flop: Transfer D to Q on falling edge of Clock
    block (Clock'EVENT and Clock = '0')
    begin
       Q <= guarded D after 5ns;
    end block;

    -- Tristate driver with input B and output A 
    block (Enable = '1')
    begin
        A <= B when GUARD = '1' else 'Z';
    end block;

Concurrent Procedure Call - Back To Top

Example

   ReadMemory (DataIn, DataOut, RW, Clk);
   (where the ReadMemory procedure is defined elsewhere)

Component instantiation - Back To Top

• In the declaration section: list the "component declaration" and one or more "configuration specifications".
  
  

The "component declaration" defines the component interface, which corresponds to the component's entity declaration. This allows the VHDL compiler to check signal compatibilities.

Example

    component adder
       port(a,b:  in  bit_vector(7 downto 0);
            s:    out bit_vector(7 downto 0);
            cin:  in  bit;
            cout: out bit);
    end component;

• The "configuration specification" identifies specific architecture(s) to be used for each instance of the component. (There may be multiple architectures for a given component.)

Examples

    for ALL:     comp1 use entity work.comp1 (equations);
    for ADDER1:  adder use entity work.adder (equations);
    for ADDER2:  adder use entity work.adder (dataflow);

In all three examples, the prefix work. indicates that the current working library contains the indicated component models. In the first example, architecture equations of entity comp1 is used for all instances of comp1. In the other examples, architecture equations is to be used for instance ADDER1 of component adder, and architecture dataflow is to be used for instance ADDER2 of component adder.

Component Instantiation Each instance of a declared component is listed, an instance name assigned, and actual signals connected to its ports as follows:

instance_name: component_name port map (port list);

• v,w, and y must be bit_vectors, y and z bits

Example

(The signal ordering is not important in this format)

Example:

    architecture r1 of register is
       component jkff
          port(J,K,CLK: in bit;
               Q,QN:    out bit);
       end component;
       for ALL: jkff use entity work.jkff (equations);
       -- Use architecture equations of entity jkff
          for all instances

       component dff
          port(D,CLK: in bit;
               Q,QN:  out bit);
       end component; 
       for DFF1: dff  use entity work.dff  (equations);
       for DFF2: dff  use entity work.dff  (circuit);
       --Use different architectures of dff for instances
         DFF1 and DFF2
    begin
       JKFF1: jkff port map (j1,k1,clk,q1,qn1);
       JKFF2: jkff port map (j2,k1,clk,q2,qn2);
       DFF1:  dff  port map (d1,clk,q4,qn4);
       DFF2:  dff  port map (d2,clk,q5,qn5);
    end.

Concurrent assertion - Back To Top

Syntax:

    assert  (clear /= '1') or (preset /= '1')
    report "Both preset and clear are set!"
    severity warning;

Generate statement - Back To Top

Example

  add_label:        -- Note that a label is required here
    for i in 4 downto 1 generate
        FA: full_adder port map(C(i-1), A(i), B(i), C(i), Sum(i));
    end generate;

The resulting code would look like:

    FA4: full_adder port map(C(3), A(4), B(4), C(4), Sum(4));
    FA3: full_adder port map(C(2), A(3), B(3), C(3), Sum(3));
    FA2: full_adder port map(C(1), A(2), B(2), C(2), Sum(2));
    FA1: full_adder port map(C(0), A(1), B(1), C(1), Sum(1));

SEQUENTIAL STATEMENTS - Back To Top

Wait statement - Back To Top

Syntax:

    wait [on signal_name {,signal_name}]
         [until condition]
         [for time expression]

Example

    wait until clock = '1' or enable /='1' for 25ns;

Signal assignment statement - Back To Top

Example

    A <= B after 10ns;
    C <= A after 10ns;  -- value of C is current A value

Variable assignment statement - Back To Top

Example

    A := B and C;
    D := A;        -- value of D is new A value

Procedure call - Back To Top

Conditional Statements - Back To Top

    if condition then
       ... sequence of statements... 
    elsif condition then
       ... sequence of statements...
    else 
       ... sequence of statements...
    end if;

    case expression is
       when choices => sequence of statements
       when choices => sequence of statements
       ...
       when others => sequence of statements
    end case;

Loop statements - Back To Top

 label: while condition loop
    ... sequence of statements ...
    end loop label;

 label:  for loop_variable in range loop
  ... sequence of statements...
   end loop label;

Loop termination statements - allow termination of one iteration, loop, or procedure.

next [when condition]; -- end current loop iteration

exit [when condition]; -- exit innermost loop entirely

return expression; -- exit from subprogram

NOTES: 1. The next/exit condition clause is optional.

2. The return expression is used for functions.

PROCEDURES - Back To Top

Example

   procedure  proc_name (signal clk: in vlbit;
                         constant d: in vlbit;
                         signal data: out vlbit) is
       ... local variable declarations ...
   begin
       ... sequence of statements ...
   end proc_name;

FUNCTIONS - Back To Top

Example

   -- Convert bit_vector to IEEE std_logic_vector format
   -- (attributes LENGTH and RANGE are described below)
   function bv2slv (b:bit_vector) return std_logic_vector is
       variable result: std_logic_vector(b'LENGTH-1 downto 0);
   begin
       for i in result'RANGE loop
           case b(i) is
               when '0' => result(i) := '0';
               when '1' => result(i) := '1';
           end case;
       end loop;
       return result;
   end;

   -- Convert bit_vector to unsigned (natural) value 
   function b2n (B: bit_vector) return Natural is
       variable S: bit_vector(B'Length - 1 downto 0) := B;
       variable N: Natural := 0;
   begin
       for i in S'Right to S'Left loop
           if S(i) = '1' then
               N := N + (2**i);
           end if;
       end loop;
       return N;
   end;

Function Calls:

       signal databus:  vector4(15 downto 0);
       signal internal: bit_vector (15 downto 0);
       variable x: integer;
        ....
       databus <= bv2slv (internal);
       x := b2n(internal);

To_bit(sul) - from std_ulogic to bit
To_bitvector(sulv) - from std_ulogic_vector/std_logic_vector
To_StdULogic(b) - from bit to std_ulogic
To_StdLogicVector(bv) - from bit_vector or std_ulogic_vector
To_StdULogicVector(bv)- from bit_vector or std_logic_vector
To_X01(v) - from bit, std_ulogic, or std_logic to X01
To_X01Z(v) - from bit, std_ulogic, or std_logic to X01Z
To_UX01(v) - from bit, std_ulogic, or std_logic to UX01

Other "ieee.std_logic_1164" functions - Back To Top

rising_edge(s) - true if rising edge on signal s (std_ulogic)
falling_edge(s) - true if falling edge on signal s (std_ulogic)

library mgc_portable;
use mgc_portable.qsim_logic.ALL;

a + b, a - b, a * b, a / b, a mod b, a rem b

Logical operations between all signal types and vectors of signal types in the "ieee" library.

and, or, nand, nor, xor, xnor, not

Shift/rotate left/right logical/arithmetic operators:

sll, srl, sra, rll, rrl

Ex. a := x sll 2; -- "shift left logical" bit_vector x by 2 bits

Relational operations: =,/=,<,>,<=,>=

Type conversion:

to_bit (from integer)
to_integer (from bit_vector)

OBJECT ATTRIBUTES - Back To Top

Signal Condition Attributes (for a signal S)

S'DELAYED(T) - value of S delayed by T time units
S'STABLE(T) - true if no event on S over last T time units
S'QUIET(T) - true if S quiet for T time units
S'LAST_VALUE - value of S prior to latest change
S'LAST_EVENT - time at which S last changed
S'LAST_ACTIVE - time at which S last active
S'EVENT - true if an event has occurred on S in current cycle
S'ACTIVE - true if signal S is active in the current cycle
S'TRANSACTION - bit value which toggles each time signal S changes

Examples

    if (clock'STABLE(0ns)) then  -- change in clock?
        ...      -- action if no clock edge
    else
        ...      -- action on edge of clock
    end if;

    if clock'EVENT and clock = '1' then
        Q <= D after 5ns;       -- set Q to D on rising edge of clock
    end if;

Data Type Bounds (Attributes of data type T)

T'BASE - base type of T
T'LEFT - left bound of data type T
T'RIGHT - right bound
T'HIGH - upper bound (may differ from left bound)
T'LOW - lower bound

Enumeration Data Types (Variable/signal x of data type T)

T'POS(x) - position number of value of x of type T
T'VAL(x) - value of type T whose position number is x
T'SUCC(x) - value of type T whose position is x+1
T'PRED(x) - value of type T whose position is x-1
T'LEFTOF(x) - value of type T whose position is left of x
T'RIGHTOF(x) - value of type T whose position is right of x

Array Indexes for an Array A (Nth index of array A)

A'LEFT(N) - left bound of index
A'RIGHT(N) - right bound of index
A'HIGH(N) - upper bound of index
A'LOW(N) - lower bound of index
A'LENGTH(N) - number of values in range of index
A'RANGE(N) - range: A'LEFT to A'RIGHT
A'REVERSE_RANGE(N) - range A'LEFT downto A'RIGHT

Examples

    for i in (data_bus'RANGE) loop
        ...
    for i in (d'LEFT(1) to d'RIGHT(1)) loop
        ...

Block Attributes (of a block B)

B'BEHAVIOR - true if block B contains no component instantiations
B'STRUCTURE - true if no signal assignment statements in block B

THE TEXTIO PACKAGE - Back To Top

use std.textio.all;

Data Types:

text - a file of character strings
line - one string from a text file

Example Declarations

   file Prog: text is in "file_name"; --text file "file_name"
   variable L: line;              -- read lines from file to L

Reading Values From a File:

readline(F, L)

Read one line from "text" file F to "line" L

 

read(L, VALUE, GOOD);

Read one value from "line" L into variable VALUE

• GOOD is TRUE if successful
• Data_type of VALUE can be bit, bit_vector, integer, real, character, string, or time.

Writing values to a file:

writeline(F, L);

Write one line to "text" file F from "line" L

 

write(L, VALUE, JUSTIFY, FIELD);

Write one value to "line" L from variable VALUE

• Data_type of VALUE can be bit, bit_vector, integer, real, character, string, or time.
• JUSTIFY is "left" or "right" to justify within the field
• FIELD is the desired field width of the written value