Case Statement
|
| Sequential Statement |
---- used in ----> |
Process
Function
Procedure |
case expression is
when choice =>
sequential statements
when choice =>
sequential statements
end case;
|
All possible choices must be included, unless the others clause is used as the last choice:
case SEL is
when "01" => Z <= A;
when "10" => Z <= B;
when others => Z <= 'X';
end case;
|
A range or a selection may be specified as a choice:
case INT_A is
when 0 => Z <= A;
when 1 to 3 => Z <= B;
when 4|6|8 => Z <= C;
when others => Z <= 'X';
end case;
|
Choices may not overlap
case INT_A is
when 0 => Z <= A;
when 1 to 3 => Z <= B;
when 2|6|8 => Z <= C; -- illegal
when others => Z <= 'X';
end case;
|
A range may not be used with a vector type
case VEC is
when "000" to "010"
=> Z <= A; -- illegal
when "111" => Z <= B;
when others => Z <= 'X';
end case;
|
| See also the null statement |
The CASE statement is generally synthesisable.
With repeated assignments to a target signal, it willsynthesise to a
large multiplexer with logic on the select inputs to evaluate the
conditions for the different choices in the case statement branches. No
"priority" will be inferred from the order of the branches
With multiple targets and embedded if statements, the case
statement may be used to synthesise a general mapping function, e.g.
next state and output generation for a finite state machine. For
example:
case READ_CPU_STATE is
when WAITING =>
if CPU_DATA_VALID = '1' then
CPU_DATA_READ <= '1';
READ_CPU_STATE <= DATA1;
end if;
when DATA1 =>
-- etc.
end case;
|
In VHDL-93, the casestatement may have an optional label:
label: case expression is
... etc.
end case label;