ICS 216, Winter 2006

Problem Set 3

Due under my office door, Friday, February 3


In this problem set you will write your own testbench for the Calc1 design used in the last problem set. You will implement test cases 1.1, 1.2, 1.3, 2.1.1, and 2.2 as described in Tables 4.5 and 4.6 in the book. Your Verilog testbench code should be organized as 5 modules, one for each test case you will implement. Each single test case may require many test stimuli sequences. Each module should be organized as follows: 1 initial block to initialize signals, 1 always block to control the clock, 1 initial block with the input stimuli, and 1 initial block containing checking code. Look at the bigtest module in the testbench of problem set 2 as a template. However, the bigtest module does not have a checking code block.

The checking block should check the output values of the Calc1 component after each test to see if the test responses are correct. Each test case should be numbered and the checking code should print out the success or failure of each test. For example, suppose that we know that out_data1 should have value hx00000000 after test 23 but it does not. The checking code should print to the screen "Test 23 failed" or "Test 23 passed" based on whether or not out_data1 is equal to hx00000000 or not.

All of this code should be well documented. I should be able to easily find the test stimuli and the checking code for each test case.

Turn in your well documented verilog testbench code and turn in a printout of the output of the checking code. Describe any bugs you find.