ICS 216: Embedded Systems Validation, Problem Set 2

ICS 216, Winter 2006

Problem Set 2

Due under my office door, Friday, January 27

Download the Calc1 and Calc2 HDL examples from the book. Simulate the Verilog code for Calc1 with the testbench provided using vcs. Generate waveforms of some of the out signals of the bigtest module (out_data1, out_resp1, out_data2, out_resp2) and turn in a screen dump of the waveforms. Be sure to include at least the first 3000 time units in the waveform screen dump. List the steps that you took to successfully generate the waveforms. Highlight any interesting problems that you had.