In this project you will design a system to perform smoothing and
downsampling, as described in lecture. Your system should take a
sequence of integer values, one at each clock cycle, which represent
an audio signal. Based on the operation selected, smoothing or
downsampling, your system should perform the operation and output a
sequence of integer values which represent the audio signal after
processing.

The smoothing filter generates an output sample by averaging the
values of the previous input samples. The number of previous input
samples which are averaged together is called the 'window size'.

For example let's 't' to refer to the time step. If the input (output)
sequence is P(Q) then P[t] (Q[t]) is the input (output) sample at time
t. If the window size is 3 then the following equation describes the Q
as a function of P:

Q[t] = (P[t-3] + P[t-2] + P[t-1]) / 3

The downsampling function reduces the sampling frequency of the input
sequence by dropping samples. The downsampling factor M is the ratio
between the old and new frequencies. Samples are dropped from the
input sequence until the output sample frequency is reduced
sufficiently. For example, to achieve a downsampling factor of 2,
every other input sample would be dropped. To achieve a downsampling
factor of 4 we would drop 3 samples for every 4 in the input stream.

The system should have the following inputs.

sample_in: This is 8 bits wide and it contains the values of the input
	   sequence. We assume that the input sampling frequency is
	   the same as the clock frequency, so sample_in should have a
	   new value every clock cycle.  

reset: This initializes the system and starts a new function, either
       smoothing or downsampling.

F/DS: This selects the operation to be performed. If this bit equals 0
      then smoothing should be performed. Otherwise, downsampling
      should be performed. Note that the value of the F/DS bit is only
      important when the reset occurs. If F/DS changes during an
      operation, the change should be ignored until reset is asserted.

ctrl: This is 3 bits wide and it selects the window size if smoothing
      is being performed, and the downsampling factor if downsampling
      is being performed. The legal window sizes are between 1, 2, and
      4. The legal downsampling factors are 1, 2, and 4.

clk: This is just the clock.

The system should have one output, sample_out, which is the 8 bit
value of the output sequence.


1. Write pseudocode to describe the system behavior. This pseudocode
   could be in Java or something like it. Turn in the pseudocode with
   your project.

2. Implement the system in Verilog in the same style as the previous project.

3. Make a testbench which performs smoothing and downsampling for the
   following sequences:

1, 2, 3, 4, 5, 6, ...
2, 4, 2, 4, 2, 4, ...
1, 5, 6, (repeat) ...