For this lab you will need to design a greatest common divisor (gcd) module in Verilog. The component should take two 8 bit numbers as inputs and generate an 8 bit number at the output which is the greatest common divisor between the two inputs. Your gcd module will also need a Reset input and a Clock input. The following algorithm describes how your module should compute the gcd.

gcd(inputs: [7:0] X, Y; output: [7:0] Z);
   register [7:0] XR, YR, TEMPR;
   XR = X;
   YR = Y;
   while XR>0 do 
   begin
      if XR≤YR then 
      begin
	TEMPR = YR;
	YR = XR;
	XR = TEMPR;
      end
      XR = XR - YR;
   end
   Z = YR;
end 

Your gcd module should be built from a Controller module and a Datapath module which are connected structurally. The Controller and Datapath should be designed as described in class. 

Create a testbench which computes the gcd of three pairs of numbers, one at a time. Be sure that the testbench prints each pair of inputs and the gcd between the pair. The gcd module should be called gcd and thefile should be called gcd.v. The testbench should be called gcd_tb and the testbench file should be called gcd_tb.v. A third file called gcd_output.txt should contain the text output generated during
simulation which will contain the input pairs and the gcd output results.