Register-Transfer Level (RTL) Design

1. RTL Design Method - (practice and understand in-class example)
   1. Capture high-level state machine
   2. Create datapath
   3. Connect datapath to controller
   4. Derive controller's FSM
2. RTL Pitfalls - Delayed register update, don't read from an output
3. Control dominated vs. Data dominated
   • What is the difference?
   • Why doesn't FIR filter need a controller?
4. Clock frequency computation, critical path
5. Converting C to gates
   1. Capture behavior in C
   2. Convert to high-level state machine
6. Memories - Know internal strucure but not transistor-level details
   • RAM - SRAM vs DRAM
   • Inputs, outputs, read/write timing diagram
   • ROM
     • Mask programmable
     • Fuse-based
     • EPROM, EEPROM, Flash
   • Queue Implementation
   • Combining small memories to make big memories