Sequential Logic Design

1. Storage Elements
   • SR latch
   • Level-sensitive SR latch
     • Clocks: period, clock cycle, frequency
   • Level-sensitive D latch
   • D flip-flop
     • Setup time, hold time
     • Metastability
     • set/reset, synchronous/asynchronous
     • Glitch prevention
   • Register
2. Finite State Machines
   • States, transitions, inputs, outputs
   • How are transitions labeled?
   • How are states labeled?
3. Controller Architecture
   • Combinational logic, state register, inputs, outputs
4. Controller Design Process
   1. Capture FSM
   2. Create architecture
   3. Encode states
   4. Create state table
   5. Implement combinational logic
5. Sequential Circuit to FSM