Some Project Ideas

• Testbench Creation: Your goal is to make a high quality test bench for a larger Verilog description. To do this project you will need to do the following:
  1. Find a working Verilog description.
  2. Completely understand the behavior of the Verilog description.
  3. Make a testbench and demonstrate rigorously that it will detect the vast majority of design errors.
  A good place to look for Verilog examples is the University of Texas at Austin 1997 Benchmark Suite . Each benchmark comes with a paper describing its behavior and a set of properties for verification.

  Demonstrating that the testbench that you create is a "complete" testbench will be tough. Be sure to use the spcification-based and coverage-based techniques that we spoke about in class. Remember that you will be graded not just on how complete your testbench is, but also on how well you can demonstrate that your testbench. You need to justify the completeness of your testbench in the paper.

• Assertion-Based Testing : The goal is to write a set of assertions in OVL and simulate them for testing. There are two variations of this project.
  1. Variation 1 - Write your own Verilog: Find a specification and write a verilog description of that specification. Create a set of assertions in OVL based on the specification. Create a testbench and simulate the design with the assertions. You will need to insert a few errors just to show that the assertions catch the errors.

     For this variation you will need to find a reasonably complex specification or take a more complicated specification and simplify it with my help. You should meet with me on how to do this. I would suggest a specification for a bus protocol (PCI, CAN) or a any popular IEEE standard like wifi (IEEE 802.11) or boundary scan (IEEE 1149.1).

     You will need to download OVL and learn how to use it with VCS. This shouldn't be to comlicated. You will need to write a testbench, but random patterns will be sufficient for this project. We can talk about the details.

  2. Variation 2 - Find existing Verilog: This is the same as the first variation except that you don't write the verilog. Instead you can find existing verilog and write assertions for it. You would need a specification accompanying the verilog to help you write the assertion. I recommend using one of the examples in the University of Texas at Austin 1997 Benchmark Suite . These examples have specifications and have a set of CTL properties which you can use to help you make the assertions.
• Model Checking: The goal is to perform model checking on a few larger verilog descriptions. I recommend using some of the examples in the University of Texas at Austin 1997 Benchmark Suite . These examples have specifications and have a set of CTL properties which you can use for model checking. You will need to verify that the set of properties given are complete, and if they are not, you will need to add new properties.