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| Instructor: |
Ian G. Harris |
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| Goals: |
Students will learn practical techniques for debugging behavioral
hardware designs. Both simulation-based and formal verification
techniques will be introduced, but the focus of the course is on the
use of simulation for functional verification. The use of hardware
simulators and debugging tools will be explored extensively. The
second half of the quarter will be devoted to student projects in
validation.
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| xxx |
| Assignments: |
There will be two problem sets during the first half of the course
and individual student projects during the second half of the course.
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| xxx |
| Time/Place: |
MW 5:00-6:20, ICS 209 |
| xxx |
| Readings: |
The required text is
Comprehensive Functional Verification, Bruce Wile, John C. Goss,
and Wolfgang Roesner, Morgan Kaufman, 2005. A book on Verilog would be
useful, including Verilog HDL A Guide
to Digital Design and Synthesis, Samir Palnitkar, Second Edition.
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| Prerequisites: |
Knowledge of hardware design
(ICS 152 equivalent). Knowledge of a hardware description
language (Verilog or VHDL) is useful but not necessary. |
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| Syllabus: |
- Hardware Simulation
- Verilog Basics
- Running the simulator
- How to use the debugger/waveform viewer
- Advanced Hardware Debugging
- Writing testbenches
- Devising test sequences
- Coverage metrics
- Manual comparison of responses
- Using assertions
- Formal Verification
- Model checking
- CTL
- Equivalence checking
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