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| Instructor: |
Ian G. Harris |
| xxx |
| Goals: |
Students will learn how to design hardware at the gate-level and
register-transfer level. Topics include coimbinational logic design,
sequential logic design, RTL design, and logic optimization.
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| xxx |
| Assignments: |
There will be no homework assignments during the course. Instead there
will be a series of 5 tests, each of equal value. No test will be
specifically designated as midterm or final.
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| xxx |
| Time/Place: |
1:00PM - 3:50 PM, DBH 1300 |
| xxx |
| Textbook: |
Digital Design , Frank
Vahid, John Wiley and Sons Inc, 2006.
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| TAs: |
There will be no TA for this course. . |
| Prerequisites: |
CS 51 or equivalent. |
| Cheating: |
Any violation of the UCI dishonesty
policy will be punished with a grade of F in the class and a report to
the Dean. |
| Tests: |
Test
schedule and syllabi . |
| Slides: |
|
| Sample Problems: |
Problems and solutions . |
| Syllabus: |
- Combinational Logic Design (Chapter 2)
- Sequential Logic Design (Chpater 3)
- RTL Component Design (Chapter 4)
- RTL Design (Chapter 5)
- Optimizations and Tradeoffs (Chapter 6)
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