Compiler-in-the-Loop, ADL-driven Early Architectural Exploration

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Aviral Shrivastava , Nikil Dutt , Alex Nicolau, and Eugene Earlie,

TECHCON 2005: Semiconductor Research Corporation

Abstract: Processor architects today critically need software tools that accurately track architectural changes made during exploration, and provide fast and quantitative feedback for each design point. Indeed, Design Space Exploration (DSE) without the compiler-in-the-loop (CIL) can be meaningless. To effectively explore the processor-memory-coprocessor design space, a system architect critically needs a compiler that can exploit the advantages of micro architectural features, hide memory latency and effectively use the coprocessor. This paper presents a CIL framework for processor architecture DSE. The framework is developed around EXPRESSION, an Architecture Description Language (ADL) that captures the functionality and structure of the processor at a high level. A software toolkit comprising an optimizing compiler, an instruction-set simulator and a cycle-accurate simulator are parameterized from the ADL, allowing for early estimation of performance, power and code size. System designers can modify the ADL to reflect architectural changes; for each change, the applications are re-evaluated using the architecture-sensitive compiler and the cycle-accurate simulator and feedback on performance as well as power is provided. Furthermore, the ADL can be used as a golden reference model for the ensuing phases of design and analysis. This paper demonstrates the need and usefulness of CIL DSE methodology for the exploration of register bypasses in the Intel XScale architecture.

Center For Embedded Computer Systems,
Department of Information and Computer Science,
University of California, Irvine.
Strategic CAD Labs,
Intel Corporation,
Hudson, Massachussets.