Energy Efficient Code Generation using rISA

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Aviral Shrivastava and Nikil Dutt

ASPDAC 2004: Proceedings of the Asia and South Pacific Design Automation Conference

Abstract: Energy consumption is emerging as a critical design concern for programmable embedded systems. Many reduced Bit-width Instruction Set Architectures (rISA) (e.g., ARM-Thumb) are being increasingly used to decrease code size. Previous work has explored energy savings in non-cached rISA architectures as a byproduct of code size reduction. In this paper we present an energy efficient code generation technique for rISA architectures, and furthermore explore energy savings for both cached and non-cached architectures. Our code generation technique uses profile information to find the most frequently executed parts of the program. By aggressively reducing code size on frequently executed parts, fewer fetches to instruction memory are incurred, thus reducing the power consumption of the instruction memory. We achieve an average 30% reduction in instruction memory energy consumption in cached systems, on a variety of benchmarks, as compared to non-rISA architectures.

Center For Embedded Computer Systems,
Department of Information and Computer Science,
University of California, Irvine.