Automatic Generation of Operation Tables for Fast Exploration of Bypasses in Embedded Processors

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Aviral Shrivastava , Sanghyun Park , Nikil Dutt , Alex Nicolau , Eugene Earlie , and Yunheung Paek

DATE 2006: Proceedings of the International Conference on Design Automation and Test in Europe.

Abstract: Customizing the bypasses in an embedded processor uncovers valuable trade-offs between the power, performance and the cost of the processor. Meaningful exploration of bypasses requires bypass-sensitive compiler. Operation Tables (OTs) have been proposed to perform bypass-sensitive compilation. However, due to lack of automated methods to generate OTs, OTs are currently manually specified by the designer. Manual specification of OTs is not only an extremely time consuming task, but is also highly error-prone. In this paper, we present AutoOT, an algorithm to automatically generate OTs from a high-level processor description. Our experiments on the Intel XScale processor model running MiBench benchmarks demonstrate that AutoOT greatly reduces the time and effort of specification. Automatic generation of OTs makes it feasible to perform full bypass exploration on the Intel XScale and thus discover interesting alternate bypass configurations in a reasonable time. To further reduce the compile-time overhead of OT generation, we propose another novel algorithm, AutoOTDB. AutoOTDB is able to cut the compile-time overhead of OT generation by half.

Center For Embedded Computer Systems,
Department of Information and Computer Science,
University of California, Irvine.
SOAR Group,
School of Electrical Engineering,
Seoul National University, Seoul, Korea.
Strategic CAD Labs,
Intel Corporation,
Hudson, Massachussets.