Course Syllabus

CompSci154 - Computer Design Lab

Prof. A. Veidenbaum

 

Prerequisites: CompSci151 (or equivalent). CompSci152 is also recommended, concurrent registration in 152 OK

Optional Textbook: Andrew Rushton, "VHDL for Logic Synthesis", McGraw Hill Publishing Co. or a similar VHDL textbook

 

Students are required to bring a laptop to class. Please make sure to have an X-window terminal installed (default for unix/macos).

 

COURSE OVERVIEW

This course is an introduction to computer system design. It examines a detailed design of major processor units, such as the register file, ALU, PC unit, memory interface, and control unit and how they work together to execute programs. It introduces students to a synthesizable subset of a hardware description language VHLD and teaches students how to design and verify a processor using the language. The use of CAD tools, specification, design and verification are also introduced. Each student designs and verifies a complete processor that can execute a subset of MIPS ISA.

 

The course assumes the knowledge of basic elements used in designing a computer system, such as combinational and sequential logic, and uses them to design an ALU, register file, memory, and the basic control for these subsystems (some of these concepts will be reviewed). The design will be done at a much higher level than logic gates and flip-flops.  In addition to teaching students the design skills, the course teaches how designs are simulated. It helps students to better understand how a processor works.

 

The course deals with design at the logic gate level or higher, not hardware design. However, using CAD tools students produce working hardware using the FPGA technology.

 

After taking this course, you should be able to:

- Better understand how a processor works

- Describe computer components using a hardware description language -

- Design all major blocks of a simple processor

               This includes an instruction cache

- Design a control unit and make a complete processor

- Learn how to verify design correctness

- Simulate program execution on your design

- Learn how to synthesize hardware from a VHDL design

 

The course is composed of two components: lectures and labs. The objective of the lectures is to introduce and help you learn VHDL and CAD tools, processor design and verification concepts. The lab has three objectives: learn to program in VHDL and use the CAD tools, review synchronous design, and introduce the design and verification of main processor components and of the complete processor. The bulk of your work will be in the lab.

 

Administivia

Instructor:  Professor A. Veidenbaum

    Office: 3056 Bren Hall

    Mail: alexv@ics

    Office Hours: Immediately after class or by appointment

 

All lab assignments will be posted on the web and must be submitted electronically via Canvas (unless specified otherwise).  Some design work will be done in the lectures.

 

Late assignments will NOT be accepted (exceptions for illness or other cases may be made, in writing, and submitted to the TA or instructor prior to due date).

 

GRADING

Your grade in CS154 will depend on your performance in class and lab assignments. The following approximate weights are going to be used:

Class attendance and participation - 5%. Class attendance is mandatory

Lab - 95%

 

Individual lab assignments carry different weights depending on the degree of difficulty, approximately 3/5/10/12/15/25.

We'll try to grade the material as quickly as possible, but grading is not instantaneous.

Lab assignment results will be posted online.

 

If you wish to have something re-graded, you MUST write a cover sheet and hand it to the TA or the instructor. Explain why you believe a problem (or problems) was mis-graded. The re-grades will only be considered for a period of 1 week following the date of the result posting.

 

Lab Assignments (Tentative)

Lab 1: Learn to use VHDL, make a simple design, test it

Lab 2: Design a sequential circuit

Lab 3: Design and verify a simple data path

Lab 4: Design and verify the basic data path

Lab 5: Add memory (for Ld/St, instruction fetch), branches, to the data path

Lab5a: Instruction cache design

Lab 6: Design a control unit for the data path (as implemented in Lab 5a), put together and verify the full processor

Synthesis Lab