Journals

Journals

J1	D.D. Gajski, N.D. Dutt and B.M. Pangrle, “Silicon Compilation,” Journal of Semicustom ICs, Vol. 4, No. 2, December 1986, pp. 5-21.
J2	N.D. Dutt and D.D. Gajski, “Design Synthesis and Silicon Compilation,” IEEE Design and Test of Computers, December 1990, pp. 8-23.
J3	N.D. Dutt, “A Language for Designer Controlled Behavioral Synthesis,” INTEGRATION: The VLSI Journal, No. 16, 1993, pp. 1-31.
J4	P.K. Jha and N.D. Dutt, “Rapid Estimation for Parameterized Components in High-Level Synthesis,” IEEE Transactions on VLSI Systems, September 1993, pp. 296-303.
J5	D.D. Gajski and N.D. Dutt, “Benchmarking and the Art of Synthesis Tool Comparison,” IFIP Transactions A: Computer Science and Technology, Vol. A-22, 1993.
J6	R. Ang and N.D. Dutt, “A Representation for the Binding of RT-Component Functionality to HDL Behavior,” IFIP Transactions A: Computer Science and Technology, Vol. A-32, 1993, pp. 263-280.
J7	N.D. Dutt and P.K. Jha, “Generic RT Component Sets for High-Level Design Applications,” VLSI Design, Vol. 5, No. 2, 1997, pp. 155-165.
J8	N.D. Dutt, R. Camposano, D. Agnew, H. Yasuura, A. Domic and M. Wiesel, “Design Reuse: Fact or Fiction?” IEEE Design and Test of Computers, Winter 1994 (ACM-SIGDA/D&T Roundtable Summary), pp. 70-77.
J9	A. Capitanio, N.D. Dutt and A. Nicolau, “Partitioning of Variables for Multiple-Register-File Architectures via Hypergraph Coloring,” IFIP Transactions: Parallel Architectures and Compilation Techniques, Vol. A-50, 1994, pp. 319-322.
J10	P.K. Jha and N.D. Dutt, “High-Level Library Mapping for Arithmetic Components,” IEEE Transactions on VLSI Systems, Vol. 4, No. 2, June 1996, pp. 1-13.
J11	A. Capitanio, A. Nicolau and N.D. Dutt, “A Hypergraph-Based Model for Port Allocation on Multiple-Register-File VLIW Architectures,” International Journal of Parallel Programming, Vol. 23, No. 6, 1995, pp. 499-513.
J12	P.K. Jha, S. Parameswaran and N.D. Dutt, “Reclocking Controllers for Minimum Execution Time,” IEICE Transactions Special Issue on VLSI Design and CAD Algorithms, Vol. E78-A, No. 12, December 1995, pp. 1715-1722.
J13	D.J. Kolson, A. Nicolau, N.D. Dutt and K. Kennedy, “Optimal Register Assignment to Loops for Embedded Code Generation,” ACM Transactions on Design Automation of Electronic Systems, Vol. 1, No. 2, April 1996.
J14	D.J. Kolson, A. Nicolau and N.D.Dutt, “Elimination of Redundant Memory Traffic in High-Level Synthesis,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, No. 11, November 1996.
J15	S.Y. Ohm, F.J. Kurdahi and N. Dutt, “A Unified Lower Bound Estimation Technique for High-Level Synthesis,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 16, No. 5, May 1997.
J16	P.R. Panda, N.D. Dutt and A. Nicolau, “Memory Data Organization for Improved Performance in Embedded Processor Applications,” ACM Transactions on Design Automation of Electronic Systems, Vol. 2, No. 4, October 1997.
J17	P.R. Panda, N.D. Dutt and A. Nicolau, “Incorporating DRAM Access Modes into High-Level Synthesis,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, No. 2, pp. 96-109, February 1998.
J18	P.R. Panda and N.D. Dutt, “Low Power Memory Mapping through Reducing Address Bus Activity,” IEEE Transactions on VLSI Systems, Vol. 7, No. 3, pp. 309-320, September, 1999.
J19	P.K. Jha and N.D. Dutt, “High-Level Library Mapping for Memories” ACM Transactions on Design Automation of Electronic Systems. Vol. 5, No. 3, pp. 566-603, July 2000.
J20	P.R. Panda, N.D. Dutt and A. Nicolau, “On-Chip vs. Off-Chip Memory: The Data Partitioning Problem in Embedded Processor-based Systems,” ACM Transactions on Design Automation of Electronic Systems. Vol. 5, No. 3, pp. 682-704, July 2000.
J21	P.R. Panda, N.D. Dutt and A. Nicolau, “Local Memory Exploration and Optimization in Embedded Systems,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, No. 1, pp. 3-12, January 1999.
J22	P.R. Panda, H. Nakamura, N.D. Dutt and A. Nicolau, “Augmenting Loop Tiling with Data Alignment for Improved Cache Performance,” IEEE Transactions on Computers, Vol. 48, No. 2, pp. 142-149, February 1999.
J23	A. Khare, P.R. Panda, N.D. Dutt, and A. Nicolau, "High-Level Synthesis with SDRAMs and RAMBUS DRAMs," IEICE Transactions Fundamentals Special Section on VLSI Design and CAD Algorithms, Vol. E82-A, No. 11, November 1999, pp. 2347-2355.
J24	H. Wang, N.D. Dutt and A. Nicolau, “Exploring Scalable Schedules for IIR Filters with Resource Constraints,” IEEE Transactions on Circuits and Systems, Part II, Vol. 46, No. 11, pp. 1367-1379, November 1999.
J25	A. Halambi, A. Khare, N. Savoiu, P. Grun, N. Dutt and A. Nicolau, "VSAT: A Visual Specification and Analysis Tool for System-On-Chip Exploration," Journal of Systems Architecture, Special Issue on Modern Methods and Tools in Digital System Design, 2000.
J26	P.R. Panda, N.D. Dutt, A. Nicolau, F. Catthoor, A. Vandecappelle, E. Brockmeyer, C. Kulkarni and E. DeGreef, "Data Memory Organization and Optimizations in Application-Specific Systems," IEEE Design and Test of Computers, Vol. 18, No. 3, May-June 2001.
J27	F. Catthoor, K. Danckaert, S. Wuytack, and N.D. Dutt, "Code Tranformations for Data Transfer and Storage Exploration Preprocessing in Multimedia Processors," IEEE Design and Test of Computers, Vol. 18, No. 3, May-June 2001.
J28	P.R. Panda, F. Catthoor, N.D. Dutt, K. Danckaert, E. Brockmeyer, C. Kulkarni, A. Vandecappelle, and P.G. Kjeldsberg, "Data and Memory Optimization Techniques for Embedded Systems," ACM Transactions on Design Automation of Electronic Systems, Vol. 6, No. 2, pp. 149-206, April 2001.
J29	N.D. Dutt, and K. Choi, “Configurable Processors for Embedded Computer,” IEEE Computer, Vol. 36, No. 1, pp. 120-123, January 2003.
J30	J. Lee, K. Choi, and N.D. Dutt, “Compilation Approach for Coarse-grain Reconfigurable Architectures,” IEEE Design and Test of Computers, Special Issue on Application Specific Processors, pp. 26-33, January/February 2003.
J31	P. Grün, N. Dutt and A. Nicolau, “Access Pattern-Based Memory and Connectivity Architecture Exploration,” ACM Transactions on Embedded Computing Systems (TECS), Vol. 2, No. 1, pp. 33-73, February 2003
J32	P. Grün, A. Halambi, N.D. Dutt, and A. Nicolau, “RTGEN: An Algorithm for Automatic Generation of Reservation Tables from Architectural Descriptions,” IEEE Transactions on VLSI Systems, pp. 731-737, August 2003.
J33	M. Mamidipaka, D. Hirschberg and N.D. Dutt, "Adaptive Low Power Encoding Techniques using Self Organizing Lists," in IEEE Transactions on VLSI Systems, Special Issue on Low Power Systems, pp. 827-834, October 2003.
J34	P. Mishra, N.D. Dutt and H. Tomiyama, "Towards Automatic Validation of Dynamic Behavior in Pipelined Processor Specifications," in Kluwer Design Automation for Embedded Systems ( DAES )., June - September 2003, Volume 8, Issue 2-3, pp. 249-265.
J35	S. Gupta, N.D. Dutt, R.K. Gupta, A. Nicolau , Dynamically Increasing the Scope of Code Motions during the High-Level Synthesis of Digital Circuits, IEE Proceedings: Computers and Digital Techniques, (Vol. 150, No.5, Sep 2003 (invited paper).
J36	S. Pasricha, S. Mohapatra, M. Luthra, N.D. Dutt and N. Venkatasubramanian, “Reducing Backlight Power Consumption for Streaming Video Applications on Mobile Handheld Devices," Special Issue of the Journal of the Korean Multimedia Society (KSSM), Vol. ISSN 12, Dec. 2003, pp. 1-13.
J37	S. Gupta ,N. Savoiu ,N.D. Dutt ,R.K. Gupta ,A. Nicolau, Using Global Code Motions to Improve the Quality of Results for High-Level Synthesis, IEEE Transactions on Computer-Aided Design, pp. 302-311, Vol 23, No. 2, Feb 2004.
J38	P. Mishra and N.D. Dutt, "Automatic Modeling and Validation of Pipeline Specifications,” ACM Transactions on Embedded Computing Systems ( TECS), Vol 3, No. 1, pp. 114-139, February 2004.
J39	P. Mishra, M. Mamidipaka and N.D. Dutt, "Processor-Memory Co-Exploration using an Architecture Description Language”, ACM Transactions on Embedded Computing Systems ( TECS ), Vol 3, No. 1, pp. 140-162, February 2004.
J40	P. Mishra, N.D. Dutt, N. Krishnamurthy, and M. Abadir, "A Top-Down Methodology for Validation of Microprocessors,” IEEE Design & Test of Computers, Mar/Apr 04.
J41	H. Tomiyama, H. Takada and N.D. Dutt, "Memory Data Organization for Low-Energy Address Buses," IEICE Transactions Fundamentals Special Section on Low-Power System LSI, IP and Related Technology, Vol. E87-C, No.4, April 2004, pp. 606-612
J42	H. Tomiyama and N.D. Dutt, "ILP-Based Program Path Analysis for Bounding Worst-Case Inter-Task Cache Conflicts," IEICE Transactions on Information and Systems, Vol. E87-D, No. 6, June 2004, pp. 1582-1587.
J43	S. Pasricha, M. Luthra, S. Mohapatra, N.D. Dutt and N. Venkatasubramanian, “Dynamic Backlight Adaptation for Low Power Handheld Devices," IEEE Design and Test of Computers, Sep/Oct 2004.
J44	M. Mamidipaka, K. Khouri, N. D. Dutt, and M. Abadir," IDAP: A Tool for High Level Power Estimation of Custom Array Structures," IEEE Transactions on Computer-Aided Design, pp. 1361-1369, Vol 23, No. 9, Sep. 2004.
J45	S. Gupta, N.D. Dutt ,R.K. Gupta ,A. Nicolau, “Coordinated Parallelizing Compiler Optimizations and High-Level Synthesis," to appear in ACM Transactions on Design Automation of Electronic Systems (ACM-TODAES).
J46	P. Mishra, N.D. Dutt, N. Krishnamurthy, M. Abadir, “A Methodology for Validation of Microprocessors using Symbolic Simulation,” to appear in International Journal of Embedded Systems.
J47	Jong-eun Lee, Kiyoung Choi, and Nikil D. Dutt, “Evaluating Memory Architectures for Media Applications on Coarse-Grained Reconfigurable Architectures,” to appear in International Journal of Embedded Systems. January/February 2005.