% Exam Template for UMTYMP and Math Department courses
%
% Using Philip Hirschhorn's exam.cls: http://www-math.mit.edu/~psh/#ExamCls
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% run pdflatex on a finished exam at least three times to do the grading table on front page.
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% These lines can probably stay unchanged, although you can remove the last
% two packages if you're not making pictures with tikz.
\documentclass[11pt]{exam}
\RequirePackage{amssymb, amsfonts, amsmath, latexsym, verbatim, xspace, setspace}
\RequirePackage{tikz, pgflibraryplotmarks}

% By default LaTeX uses large margins.  This doesn't work well on exams; problems
% end up in the "middle" of the page, reducing the amount of space for students
% to work on them.
\usepackage[margin=1in]{geometry}
\usepackage{afterpage}

% Here's where you edit the Class, Exam, Date, etc.
\newcommand{\class}{CS 250P}
\newcommand{\term}{Fall 2019}
\newcommand{\examnum}{Midterm}
\newcommand{\examdate}{11/13/2019}
\newcommand{\timelimit}{3:30pm - 4:50pm}

% For an exam, single spacing is most appropriate
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% For an exam, we generally want to turn off paragraph indentation
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\begin{document} 

% These commands set up the running header on the top of the exam pages
\pagestyle{head}
\firstpageheader{}{}{}
\runningheader{\class}{\examnum\ - Page \thepage\ of
\numpages}{\fbox{\rule{2in}{0pt}\rule[-0.5ex]{0pt}{5ex}}}
\runningheadrule

\begin{flushright}
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%\textbf{\class} & \textbf{Name (Print):} & \makebox[2in]{\hrulefill}\\
  \textbf{\class} & \textbf{Name (Print):} &
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%\begin{minipage}[t]{3.7in}
%\vspace{0pt}
\begin{itemize}

\item \textbf{Don't forget to write your name on this exam.} 

\item \textbf{This is an open book, open notes, open electronics exam. But no online or 
    in-class communication, and no Internet search. } 

    
\item \textbf{Ask us if something is confusing in the questions.}

\item \textbf{Organize your work}, in a reasonably neat and coherent way, in
the space provided. Work scattered all over the page without a clear ordering will 
receive very little credit.  

\item \textbf{Mysterious or unsupported answers will not receive full
credit}.  A correct answer, unsupported by explanation will receive no credit; 
an incorrect answer supported by substantially correct explanations might still 
receive partial credit.

\item If you need more space, use the back of the pages; clearly indicate when you have done this.
\end{itemize}

%Do not write in the table to the right.
%\end{minipage}
%\hfill

%\begin{minipage}[t]{2.3in}
%\vspace{0pt}
%\cellwidth{3em}
%\gradetablestretch{2}
\vqword{Problem}
\addpoints % required here by exam.cls, even though questions haven't started yet.	
\gradetable[v]%[pages]  % Use [pages] to have grading table by page instead of question

%\end{minipage}
\newpage % End of cover page

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%
% See http://www-math.mit.edu/~psh/#ExamCls for full documentation, but the questions
% below give an idea of how to write questions [with parts] and have the points
% tracked automatically on the cover page.
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\begin{questions}

\newpage \addpoints

\question Basics of CPU instruction set

\begin{parts}

\part[5] Write a simple assembly program that computes factorial of N, i.e., 
	the product of all positive integers less than or equal to N. You can use any instruciton 
	set you know (e.g., x86 or RISC), you don't have to be precise (the sketch of the code will work)

\vfill

\end{parts}

\question Basics of digital design

\begin{parts}

\part[5] Design a logical circuit that adds two two-bit numbers. Make sure that an additional output 
signals the overflow. 

\vfill

\end{parts}


\newpage \addpoints

\question Pipelines and stalls


\begin{parts}

\part[5] Consider a 32-bit in-order pipeline with full bypassing that has the following stages: 

\begin{verbatim}
Fetch   Decode/Regread   IntALU     Writeback 
                         IntALU     Datamem      Datamem       Writeback 
                         FPALU1     FPALU2       Writeback
\end{verbatim}


After decode, Int-adds go through the stages labeled "IntALU" and "Writeback",
	loads/stores go through the stages labeled "IntALU", "Datamem",
	"Datamem", and "Writeback", while FP-adds go through the stages labeled
	"FPALU1", "FPALU2", and "Writeback". 
	
How many stall cycles are introduced between the following pairs of successive
	instructions (remember, the processor implements full bypassing)?

(i) Int-add, providing the address for a load/store, 

\vfill
	
(ii)  Load, providing the data for an FP-add  

\vfill 
	
(iii) Load, providing the data for a store, 

\vfill

(iv) FP-add, followed by dependent FP-add.

\vfill

\end{parts}


\addpoints

\newpage

\question Branch delay slot

Consider a 7-stage in-order processor, where the instruction is fetched in the first stage, and the branch outcome is known after 3 stages. Estimate the CPI (cycles per instruction) of the processor under the following scenarios (assume that all stalls in the processor are branch-related and branches account for 20\% of all executed instructions, assume that all branches are taken 60\% of the time and not-taken 40\% of the time).


\begin{parts} 

\part[5] On every branch, fetch is stalled until the branch outcome is known.

\vfill

\part[5] Every branch is predicted not-taken and the mis-fetched instructions are squashed if the branch is taken.

\vfill

\part [5] The processor has two delay slots and the two instructions following the branch are always fetched and executed, and
        You are able to move three instructions before the branch into the delay slot. 

\vfill

\end{parts}

\newpage
\question Loop unrolling

Consider a basic in-order pipeline with bypassing (one instruction in each pipeline stage in any cycle). The pipeline has been extended to handle FP add and FP mult. Assume the following delays between dependent instructions:

\begin{itemize}
    \item Load feeding any instruction: 3 stall cycles
    \item FP ALU feeding any instruction (except stores): 4 stall cycles
    \item FP MULT feeding any instruction (except stores): 7 stall cycles
    \item FP ALU feeding store: 3 stall cycles
    \item Int add feeding any instruction: 0 stall cycles
    \item A conditional branch has 1 delay slot (an instruction is fetched in the cycle after the branch without knowing the outcome of the branch and is executed to completion) 
\end{itemize}

Below is the source code and default assembly code for a loop.

Source Code:
\begin{verbatim}
for (i=1000; i>0; i--) {
    x[i] = y[i] + z[i];
} 
\end{verbatim}

Assembly Code:

\begin{verbatim}
Loop:
    L.D F1, 0(R2) // Get y[i]
    L.D F2, 0(R3) // Get z[i]
    ADD.D F3, F2, F1 // Add the two numbers
    S.D F3, 0(R4) // Store the result into x[i]
    DADDUI R2, R2, #-8 // Decrement R2
    DADDUI R3, R3, #-8 // Decrement R3
    DADDUI R4, R4, #-8 // Decrement R4
    BNE R2, R1, Loop // Check if we've reached the end of the loop
    NOP 
\end{verbatim}

\begin{parts}

\part[5]  Show the schedule (what instruction issues in what cycle) for the default code.

\vfill

\newpage

\part[5]  How should the compiler order instructions to minimize stalls (without unrolling) (note that the execution of a NOP instruction is effectively a stall)? Show the schedule. How many cycles can you save per iteration, compared to the default schedule?

\vfill

\part[5]  How many times must the loop be unrolled to eliminate stall cycles? Show the schedule for the unrolled code.

\vfill

\end{parts} 

\newpage

\addpoints 

\question Branch prediction

The following ``for'' loop executes inside an infinite while loop. The inner
``for'' loop executesfive iterations and has a branch inside.  

\begin{verbatim}  
while (1) {

    for (i = 0; i < 10; i++) { 
    
        if ((i & 1) == 0) {
            ...
        } 
    }
    ...
} 
\end{verbatim}


\begin{parts}

\part[5] Assume that your CPU is using a 2-bit saturating counter predictor.
Provide the pattern of branch prediction decisions by the predictor (assume
that the external while loop ran for 100 iterations already, and the counters
are in the steady state). What is the prediction success rate? I.e., out of 20
branches executed in one iteration of the inner ``for'' loop, what fraction is
predicted correctly?  

\vfill 

\newpage

\part[5] Imagine you implement a local history predictor (you're free to choose 
history size). How does this change the accuracy of the branch prediction? 

\vfill 

\end{parts}

\addpoints 

\question Out-of-order execution

\begin{parts}

\part[10]

	Consider an out-of-order processor similar to the one described in class. The architecture has 32 logical registers and 42 physical registers. On power up, the following program starts executing (to simplify the problem, some of the initialization code is not shown and you can ignore that code).

\begin{verbatim}

line1: L.D LR1 0(LR2)
       ADD.D LR1, LR1, LR1
       ST.D LR1, 0(LR2)
       ADD.D LR2, LR2, 8
       BNE LR2, LR3, line1
\end{verbatim}


The processor has a width of 4, i.e., every pipeline stage can move 4 instructions through in every cycle. Show the renamed code for the first 20 instructions of this program. How soon will the 20th instruction get committed?

Assumptions:

Assume that branch prediction is perfect for a simple program like this. With
	the help of a trace cache, even fetch is perfect. Assume that caches
	are perfect as well. Assume that the dependent of an ADD.D instruction
	can leave the issue queue in the cycle right after the ADD.D. Assume
	that the dependent of an L.D cannot leave in the next cycle, but the
	cycle after that. Assume a ROB, an issue queue, and an LSQ with 20
	entries each. When the thread starts executing, its logical register
	LR1 is mapped to physical register PR1, LR2 is mapped to PR2, and so
	on. An instruction goes through 5 pipeline stages before it gets placed
	in the issue queue and an additional 5 pipeline stages (6 for a LD/ST)
	after it leaves the issue queue (in other words, an instruction will
	take a minimum of 11 cycles to go through the pipeline). When
	determining if a L.D can issue, you need not check to see if previous
	store addresses have been resolved (just to make the problem simpler).
	
\newpage	
	\vfill 
	
	\newpage

\begin{verbatim}
	
\end{verbatim}

\end{parts}




\newpage 

\addpoints


\end{questions}
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\end{document}
