% Exam Template for UMTYMP and Math Department courses
%
% Using Philip Hirschhorn's exam.cls: http://www-math.mit.edu/~psh/#ExamCls
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% run pdflatex on a finished exam at least three times to do the grading table on front page.
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% These lines can probably stay unchanged, although you can remove the last
% two packages if you're not making pictures with tikz.
\documentclass[11pt]{exam}
\RequirePackage{amssymb, amsfonts, amsmath, latexsym, verbatim, xspace, setspace}
\RequirePackage{tikz, pgflibraryplotmarks}

% By default LaTeX uses large margins.  This doesn't work well on exams; problems
% end up in the "middle" of the page, reducing the amount of space for students
% to work on them.
\usepackage[margin=1in]{geometry}
\usepackage{afterpage}

% Here's where you edit the Class, Exam, Date, etc.
\newcommand{\class}{CS 250P}
\newcommand{\term}{Fall 2019}
\newcommand{\examnum}{Final}
\newcommand{\examdate}{12/09/2019}
\newcommand{\timelimit}{4:00pm - 6:00pm}

% For an exam, single spacing is most appropriate
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% For an exam, we generally want to turn off paragraph indentation
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\begin{document} 

% These commands set up the running header on the top of the exam pages
\pagestyle{head}
\firstpageheader{}{}{}
\runningheader{\class}{\examnum\ - Page \thepage\ of
\numpages}{\fbox{\rule{2in}{0pt}\rule[-0.5ex]{0pt}{5ex}}}
\runningheadrule

\begin{flushright}
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%\textbf{\class} & \textbf{Name (Print):} & \makebox[2in]{\hrulefill}\\
  \textbf{\class} & \textbf{Name (Print):} &
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\textbf{\term} &&\\
\textbf{\examnum} &&\\
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\textbf{Time Limit: \timelimit} & & \\
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\rule[1ex]{\textwidth}{.1pt}




%\begin{minipage}[t]{3.7in}
%\vspace{0pt}
\begin{itemize}

\item \textbf{Don't forget to write your name on this exam.} 

\item \textbf{This is an open book, open notes exam. But no online or 
    in-class chatting.  } 

    
\item \textbf{Ask us if something is confusing in the questions.}

\item \textbf{Organize your work}, in a reasonably neat and coherent way, in
the space provided. Work scattered all over the page without a clear ordering will 
receive very little credit.  

\item \textbf{Mysterious or unsupported answers will not receive full
credit}.  A correct answer, unsupported by explanation will receive no credit; 
an incorrect answer supported by substantially correct explanations might still 
receive partial credit.

\item If you need more space, use the back of the pages; clearly indicate when you have done this.
\end{itemize}

%Do not write in the table to the right.
%\end{minipage}
%\hfill

%\begin{minipage}[t]{2.3in}
%\vspace{0pt}
%\cellwidth{3em}
%\gradetablestretch{2}
\vqword{Problem}
\addpoints % required here by exam.cls, even though questions haven't started yet.	
\gradetable[v]%[pages]  % Use [pages] to have grading table by page instead of question

%\end{minipage}
\newpage % End of cover page

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%
% See http://www-math.mit.edu/~psh/#ExamCls for full documentation, but the questions
% below give an idea of how to write questions [with parts] and have the points
% tracked automatically on the cover page.
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\begin{questions}

% Basic question
\addpoints
\question Bypassing

Consider the following in-order pipeline with \textbf{bypassing}:

\begin{verbatim}
Bpred:I-cache:I-cache:Decode:Decode:Regrd:IntAdd:WB
                                   :Effadd:Dcache:Dcache:WB
                                   :FPA1:FPA2:FPA3:FPA4:WB
\end{verbatim}

After register-read, Integer-adds go through ``IntAdd'' and ``WB'' (register
writeback). Loads and stores go through ``Effadd'' (to calculate the effective
address for the load/store), then two data-cache stages, and finally the ``WB''
stage. Floating-point adds go through four ``FPA'' stages and then ``WB''. 

\begin{parts}

\part[10] How many stall cycles are introduced between the following pairs of
successive instructions? 

\begin{enumerate} 

\item Int-add, providing the data for a store

\item Int-add, providing the input for an Int-add

\item Load, providing data for an Int-add

\item FP-add, followed by a dependent FP-add

\item FP-add, providing the data for a store 


\end{enumerate}

\vfill

\end{parts}

\newpage
\addpoints
\question Branch predictors

Consider the following tournament branch predictor that employs a selector with
	8K entries (3-bit saturating counters).  The selector picks a
	prediction out of either a global predictor (12-bit global history is
	XOR-ed with 12 bits of branch PC to index into 3-bit saturating
	counters) or a local predictor (8 bits of branch PC index into level-1
	10 bits of local history are concatenated with 2 bits of branch PC to
	generate the index into level-2 that has 2-bit saturating counters).

\begin{parts}

\part[10]	What is the total capacity (size of all data structures) of the entire
	branch prediction system?


	
\vfill

\end{parts}

\addpoints
\newpage 

\question Caches


\begin{parts}

\part[5] An 8 MB L2 cache has a 64 byte line (block) size and is 8-way
	set-associative. How many sets does the cache have? How many bits are
	used for the offset, index, and tag, assuming that the CPU provides
	64-bit virtual addresses? How large is the tag array? (Be specific, and
	provide explanations for each step). 

\vfill

\end{parts}

\newpage
\addpoints



% Basic question
\addpoints

\newpage 

\question Virtual memory

\begin{parts}

\part[10] Imagine you're running an Intel 64bit server that uses a four-level
	page table where 1) each page is 4096 bytes, 2) each entry in the page
	table page is 8 bytes (512 entries per page), and 3) the translation is
	done with the following algorithm: each virtual address is split into 5
	parts, the top 9 bits index into the page-level directory (PL4) to
	choose an entry that provides address of the PL3 page, next 9 bits
	index into PL3 to choose an entry that provides a physical address of
	the PL2 page, next 9 bits index into PL2 to choose the physical address
	of PL1, next 9 bits choose an entry into PL1 that provides the physical
	address of the page, finally the last 12 bits of virtual address choose
	the byte on the page.
	
	Assume that machine has the following caching hierarchy: 1) 32 KB L1
	cache with 3 cycles latency of access, 2) 1MB L2 cache with 12 cycles
	latency of access, and 3) 22MB L3 cache with 45 cycles access latency.
	Finally, each memory access takes 250 cycles. 

	Imagine your workload constrantly reads data from random locations of
	164GBs of RAM. Estimate latency of each memory access including
	overheads of virtual to physical translation.  
	
\vfill

\end{parts}

\addpoints
\newpage

\question Out-of-order execution. 

Consider an out-of-order processor similar to the one described in class. 
The assumptions are re-stated below.  The only notable changes
are (i) that the architecture has 32 logical registers and 34 physical
registers,  and (ii) the processor has a width of 2 (only up to two instructions
can be fetched, decoded, renamed, issued, committed in a cycle). On power up,
the following program starts executing (to simplify the problem, some of the
initialization code is not shown and you can ignore that code).

\begin{verbatim}
L.D    R1, 0(R2)
L.D    R3, 0(R4)
ADD.D  R1, R1, R3
ADD.D  R2, R2, R4
BNE    R2, R4, brtarget
ADD.D  R2, R1, R3
\end{verbatim}

Assumptions: Assume that branch prediction is perfect for a simple program like
this. With the help of a trace cache, even fetch is perfect. Assume that caches
are perfect as well. Assume that the dependent of an ADD.D instruction can
leave the issue queue in the cycle right after the ADD.D. Assume that the
dependent of an L.D cannot leave in the next cycle, but the cycle after that.
Assume a ROB, an issue queue, and an LSQ with 20 entries each.  When the thread
starts executing, its logical register LR1 is mapped to physical  register PR1,
LR2 is mapped  to PR2,  and so on.   An instruction  goes through 5 pipeline
stages before it gets placed in the issue queue and an additional 5 pipeline
stages (6 for a LD/ST) after it leaves the issue queue (in other words, an
instruction will take a minimum of 11 cycles to go through the pipeline).  When
determining if a L.D can issue, you need not check to see if previous store
addresses have been resolved (just to makethe problem simpler).


\begin{parts}


\part[5] Show the renamed version of this code.

\vfill

\newpage
\part[15] Show when each instruction gets placed in the issue queue, leaves the
	issue queue, completes, and commits. 
 

\vfill

\end{parts}


\newpage 
\addpoints

\question Coherence protocols

(i) Consider a symmetric shared-memory multiprocessor (3 processors sharing a
bus) implementing a snooping cache coherence protocol such as the one discussed
in class. The protocol uses three states for each cache block (Modified,
Shared, Invalid). For each of the events below, explain the coherence protocol
steps and mention the eventual state of the data block in the caches of each of
the 3 processors. At the start, block X is not in any of the caches. 


\begin{parts}

\part[10] 

\begin{enumerate}

\item P1: Write X

\item P1: Write X

\item P2: Read X

\item P1: Read X

\item P3: Write X

\item P3: Read X

\end{enumerate} 


\vfill

\end{parts}


\addpoints

\newpage

\question Loop scheduling

Consider a basic in-order pipeline with bypassing (one instruction in each
pipeline stage in any cycle). The pipeline has been extended to handle FP and
FP mult. Assume the following delays between dependent instructions: 

\begin{enumerate}

\item Load feeding any instruction: 2 stall cycles

\item FP ALU feeding any instruction (besides stores): 3 stall cycles

\item FP MULT feeding any instruction (besides stores): 6 stall cycles

\item FP ALU feeding store: 2 stall cycles

\item Int add feeding any instruction: 0 stall cycles

\item A conditional branch has 1 delay slot (an instruction is fetched in the
cycle after the branch without knowing the outcome of the branch and is
executed to completion)

\end{enumerate}

Below is the source code and default assembly code for a loop

\begin{verbatim}
    Assembly code                               C source code

Loop: L.D       F2, 0(R1)                  for(i = 999; i >= 0; i--) {
      MULT.D    F3, F2, F1                     x[i] = y[i]*s
      S.D       F3, 0(R2)                  }
      DADDUI    R1, R1, #-8
      DADDUI    R2, R2, #-8
      BNE       R1, R3, Loop
      NOP
\end{verbatim}

\begin{parts} 

\part[3] Show the schedule (what instruction issues in what cycle) for the default code

\newpage
\vfill

\part[4]  How should  the  compiler  order  instructions  to  minimizestalls  (without  unrolling)?   Show  theschedule. How many cycles can you save per iteration, compared to the default schedule?


\vfill 

\part[8] How many times must the loop be unrolled to eliminate stall cycles?  Show the schedule for the unrolled code?

\vfill

\part[5] Show the software pipelined version of the code. 

\vfill

\end{parts}

\addpoints
\newpage

\question Side channel attacks

\begin{parts}

\part[15] Sketch the code that executes the Meltdown attack. Be specific and provide explanations. You can use 
pseudo-code for implementing both low and high-level parts of the attack. You should use exception suppression 
technique that relies on training the branch predictor. 

\vfill 


\end{parts}


\newpage 

\addpoints


\end{questions}
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\end{document}
