The growth in uniprocessor (single core) performance resulting from improvements in semiconductor technology has recently slowed down significantly. Sequential applications or sequential portions of parallel applications require further advances to improve their performance. Today's OOO processors complete instructions in their program order, which is a major performance bottleneck because any long-latency instruction, such as access to memory, delays the completion of all subsequent instructions. This project aims to achieve higher single core performance by defining a new, compiler assisted mechanism for out of order instruction completion. It investigates how the use of compile-time program knowledge can be passed to the hardware and be used to simplify the architectural checks required for such out of order completion. The architecture of a standard processor will be fully preserved and legacy software can execute without modification.

Supported by the National Science Foundation