Research

Ph.D. Thesis

Compiler-in-the-Loop Exploration of Programmable Embedded Systems

Increasing complexity of embedded systems, and shortening time-to-market makes designer productivity the key concern in embedded system development. As a result Programmable Embedded Systems - that have a programmable processor and memory subsystem to support the software part of the application - are becoming an attractive platforms for embedded system design. Programmable embedded systems greatly enhance design reuse, reduce design complexity, and time-to-market via software. The application-specific, strict, multi-dimensional design constraints, result in embedded processor designs being highly customized. Embedded processors often feature design idiosyncracies, custom-algorithms, and sometimes even miss some architectural features. Consequently, code generation for the embedded processors is a challenging task. However, if the compiler is able to exploit the architectural features of the embedded processors, it can make a tremendous difference in the power, performance, etc. of the eventual system. Existing embedded system design/exploration techniques either do not consider compiler effects on the design, or include the compiler effects in an ad-hoc manner, which may lead to inaccurate evaluation of design choices and therefore result in suboptimal design decisions.

This thesis proposes a Compiler-in-the-Loop Exploration approach, - systematic method to include compiler effects during architectural evaluation of embedded systems. This dissertation demonstrates the need and usefulness of the proposed methodology at several levels of embedded system design abstraction: at the the instruction set architecture level, at the processor pipeline design level, at the memory design level, and at the processor-memory interface level. At each level of design abstraction, this dissertation demonstrates that the proposed methodology results in a more meaningful exploration of design space leading to better design decisions with respect to the design goals of performance, code size, energy and power consumption.

Advisors: Prof. Nikil Dutt (Chair), Prof. Alex Nicolau, Prof. Alex Veidenbaum,

Software

PBExplore : A Compiler-in-the-Loop Framework to explore Register Bypasses in Pipelined Embedded Processors.
EXPRESSION : An Architecture Description Language (ADL) based Retargetable Compiler-Simulator toolchain.

Conference Papers

[DBLP]

[ACM Portal]

[IEEE Explore]

		Bypass Aware Instruction Scheduling for Register File Power Reduction NEW with Sanghyun Park, Nikil Dutt, Alex Nicolau, Eugene Earlie, and Yunheung Paek LCTES 2006 :Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers and tool support for embedded systems
		Automatic Generation of Operation Tables for Fast Exploration of Bypasses in Embedded Processors NEW with Sanghyun Park, Nikil Dutt, Alex Nicolau, Eugene Earlie, and Yunheung Paek DATE 2006 :Proceedings of the International Conference on Design Automation and Test in Europe
		Compilation Techniques for Energy Reduction in Horizontally Partitioned Cache Architectures NEW with Ilya Issenin and Nikil Dutt CASES 2005 :Proceedings of the 2005 International Conference on Compilers, Architectures and Synthesis for Embedded Systems on Hardware/Software Codesign and System Synthesis
		Aggregating Processor Free Time for Energy Reduction NEW with Eugene Earlie, Nikil Dutt, and Alex Nicolau CODES+ISSS 2005 :Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
		PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors with Eugene Earlie, Nikil Dutt, and Alex Nicolau DATE 2005 :Proceedings of the International Conference on Design Automation and Test in Europe
		Compiler-in-the-Loop, ADL-driven Early Architectural Exploration with Nikil Dutt, Alex Nicolau, and Eugene Earlie TECHCON 2005 :Semiconductor Research Corporation
		Operation Tables for Scheduling in the Presence of Partial Bypassing with Eugene Earlie, Nikil Dutt, and Alex Nicolau CODES+ISSS 2004 :Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis
		Energy Efficient Code Generation using rISA with Partha Biswas, Ashok Halambi, Nikil Dutt, and Alex Nicolau ASPDAC 2004 :Proceedings of the Asia and South Pacific Design Automation Conference
		A Design Space Exploration Framework for Reduced Bit-width Instruction Set Architecture (rISA) Design with Ashok Halambi, Partha Biswas, Nikil Dutt, and Alex Nicolau ISSS 2002 :Proceedings of the International Symposium on System Synthesis
		An Efficient Compiler Technique for Code Size Reduction using Reduced Bit-width ISAs with Ashok Halambi, Partha Biswas, Nikil Dutt, and Alex Nicolau DATE 2002 :Proceedings of the International Conference on Design Automation and Test in Europe
		A Customizable Compiler Framework for Embedded Systems with Ashok Halambi, Nikil Dutt, and Alex Nicolau SCOPES 2001 :International Workshop on Software and Compilers for Embedded Systems
		Optimal Hardware/Software Partitioning for Concurrent Specification Using Dynamic Programming with Mohit Kumar, Sanjeev Kapoor, Shashi Kumar, and M. Balakrishnan VLSI 2000 :Proceedings of the 13th International Conference on VLSI Design

Journal Articles

	ADL-driven Software Toolkit Generation for Architectural Exploration of Programmable SOCs NEW with Prabhat Mishra, and Nikil Dutt TODAES :ACM Transactions on Design Automation of Electronic Systems
	Retargetable Pipeline Hazard Detection for Partially Bypassed Processors NEW with Nikil Dutt, Alex Nicolau, and Eugene Earlie TVLSI :IEEE Transactions on VLSI
	Compilation Framework for Code Size Reduction using Reduced Bit-width ISAs with Ashok Halambi, Partha Biswas, Nikil Dutt, and Alex Nicolau TODAES :ACM Transactions on Design Automation of Electronic Systems

Selected Talks

Compiler Optimizations for Performance and Energy Improvements in Simple In-order Processors
MMDC, Intel: Massachussets Microprocessor Development Center, Intel
Hudson MA, May 2006

Compiler-in-the-Loop Exploration of Programmable SoCs
OCASA 2005: Optimizing Compiler Assisted SoC Assembly Workshop
San Francisco CA, September 2005

Compiler-in-the-loop Design Space Exploration of XScale Microarchitectures using EXPRESSION
SCL, Intel: Strategic CAD Labs, Intel
Hilsboro OR, December 2003

Co-Authors

Nikil Dutt (UCI)
Alex Nicolau (UCI)
Eugene Earlie (Intel)
Ashok Halambi (Poseidon Design Systems)
Partha Biswas (UCI)
Ilya Issenin (UCI)
Prabhat Mishra (UFL)
Sanjeev Kapoor (IIT Delhi)
Shashi Kumar (Jonkoping University, Sweden)
M. Balakrishnan (IIT Delhi)
Sanghyun Park (SNU Korea)
Yunheung Paek (SNU Korea)
Mohit Kumar (Deutsche Bank)