Task-level partitioning and scheduling for reconfigurable systems

Key Researcher: Sudarshan Banerjee

Hardware-Software (HW-SW) partitioning is a critical step in codesign of embedded systems- key system parameters such as execution time, power consumption etc., are primarily influenced by partitioning decisions. SRAM-based FPGAs are becoming popular for HW implementation and design sizes are increasing very rapidly. In this context, there is a need to investigate efficient and scalable partitioning and scheduling algorithms that do a very rapid and high-quality exploration of the design space. One key feature of modern FPGAs is dynamic reconfiguration where the hardware configuration can be changed dynamically to obtain better performance at lower hardware cost. While this is a very powerful feature,  it introduces a lot of architectural constraints on the system. We are developing a number of partitioning and scheduling algorithms to generate high-quality results in the context of multiprocessor SOCs.

Publications

S. Banerjee, N. Dutt, "Efficient Search Space Exploration for HW-SW Partitioning", CODES+ISSS, Stockholm, 2004.

Home | Projects | Publications | News & Events | People | Sponsors | Downloads | Links | Join ACES | About Us