 |
|
|
 |  |  |  |  |  |  |  |  |  |  |  |
|
Architecture Aware Compilation for Embedded Systems |
|
Modern
embedded processors are incorporating several dynamic schemes (e.g. dynamic
scheduling, caches, predication) to meet the ever tightening,
multi-dimensional demands of embedded applications. However the complex and
dynamic nature of these architectural and micro-architectural techniques
renders them intractable for exploitation by conventional compiler
technology. Our research attempts to model and exploit these dynamic
mechanisms within such processors during the process of code generation. We
investigate compilation strategies for performance, power and code size,
while allowing for exploration and evaluation of different
micro-architectural features. |
|
Publications |
|
A. Shrivastava, E. Earlie, N. Dutt, A. Nicolau "Operation Tables for Scheduling in the
Presence of Incomplete
Bypassing", CODES+ISSS' 2004. |
|
Home | Projects | Publications | News & Events | People | Sponsors | Downloads | Links | Join ACES | About Us |
Please e-mail your comments and suggestions to Sudeep Pasricha
(sudeep@ics.uci.edu) © Copyright 1997-2004 ACES-UCI. All rights reserved |
