isegen

Generation of High-Quality Instruction Set Extensions (ISEGEN)

Key Researcher: Partha Biswas

Customization of processor architectures through Instruction Set Extensions (ISEs) is an effective way to meet the growing performance demands of embedded applications. A high-quality ISE generation approach needs to obtain results close to those obtained by experienced designers, particularly for complex applications that exhibit regularity: expert designers are able to exploit manually such regularity in the data flow graphs to generate high-quality ISEs. Our ISEGEN approach identifies high-quality ISEs by iterative improvement following the basic principles of the well-known Kernighan-Lin (K-L) min-cut heuristic. Experimental results on a number of MediaBench, EEMBC and cryptographic applications show that our approach matches the quality of the optimal solution obtained by exhaustive search. We also show that our ISEGEN technique is on average 20X faster than a genetic formulation that generates equivalent solutions. Furthermore, the ISEs generated by our technique exhibit 35% more speedup than the genetic solution on a large cryptographic application (AES) by effectively exploiting its regular structure.

Publications

P. Biswas, S. Banerjee, N. Dutt, L. Pozzi and P. Ienne, "Fast Automated Generation of High-Quality Instruction Set Extensions for Processor Customization", Workshop on Application Specific Processors (WASP), 2004.

P. Biswas, V. Choudhary, K. Atasu, L. Pozzi, P. Ienne and N. Dutt, "Introduction of Local Memory Elements in Instruction Set Extensions", Design Automation Conference (DAC), 2004.