Power Estimation of Low-Power High-Performance Memory Structures (eCACTI)

Key Researcher: Mahesh Mamdipaka

This project investigates power modeling of custom memory structures at different levels of abstraction. With increasing memory content in systems, their percentage contribution to total power dissipation is predicted to further increase in future technologies. We have developed a generic methodology and models for estimation of power dissipation in array structures at different levels of the design hierarchy. At the transistor level, we developed a generic methodology to generate characterization based analytical power models for array structures. At the Register Transfer level (RT level), we developed an estimation tool named Implementation Dependent Array Power estimator (IDAP) that estimates power dissipation based on a high-level design description of the memory arrays. IDAP estimates both leakage and dynamic power dissipation in array structures. Finally, at the micro-architecture level, we developed eCACTI (enhanced CACTI), a tool that (a) estimates the power dissipation in caches, and (b) determines the optimal cache configuration that best meets the optimization criterion.

Publications

M. Mamidipaka, K. Khouri, N. Dutt, M. Abadir, "IDAP: A Tool for High Level Power Estimation of Custom Array Structures ", IEEE Transactions on CAD (TCAD), Sept. 2004.
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M. Mamidipaka, K.  Khouri, N. Dutt, M. Abadir, "Analytical Models for Leakage Power Estimation of Memory Array Structures", Proc. of Int'l Conference on Hardware/Software and Co-design and System Synthesis (CODES+ISSS), Stockholm, Sweden, Sep 2004.
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