SoC Communication Design Space Exploration and Synthesis (COMMEX)

Key Researcher: Sudeep Pasricha

Modern Systems-on-Chip are increasingly becoming more and more complex. Communication between on-chip components frequently becomes a bottleneck due to the numerous inter-component data dependencies inherent in these complex systems. Designers need to explore communication architectures to meet system performance requirements and satisfy the ever shrinking time-to-market constraints. Our main focus is on developing a methodology for modeling SoC designs for early exploration, power/performance tradeoff analysis and synthesis of the communication architectures in modern SoC designs. 

Publications

S. Pasricha, N. Dutt, "COSMECA: Application Specific Co-Synthesis of Memory and Communication Architectures for MPSoC", Design Automation and Test in Europe Conference (DATE 2006), Munich, Germany, March 2006

S. Pasricha, N. Dutt, M. Ben-Romdhane, "Constraint-Driven Bus Matrix Synthesis for MPSoC", To appear at ASPDAC 2006, Yokohama, Japan, January 2006 (BEST PAPER AWARD)

S. Pasricha, N. Dutt, E. Bozorgzadeh, M. Ben-Romdhane, "Floorplan-aware Automated Synthesis of Bus-based Communication Architectures", DAC 2005, Anaheim, CA, June 2005 (BEST PAPER AWARD CANDIDATE)

S. Pasricha, N. Dutt, M. Ben-Romdhane, "Automated Throughput-driven Synthesis of Bus-based Communication Architectures", ASP-DAC 2005, Shanghai, China, January 2005

S. Pasricha, N. Dutt, M. Ben-Romdhane, "Fast Exploration of Bus-based On-chip Communication Architectures", CODES+ISSS 2004, Stockholm, Sweden, September 2004

S. Pasricha, N. Dutt, M. Ben-Romdhane, "Extending the Transaction Level Modeling Approach for Fast Communication Architecture Exploration", DAC 2004, San Diego, CA, June 2004

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